\doxysection{DMAMUX\+\_\+\+Channel\+Status\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_d_m_a_m_u_x___channel_status___type_def}{}\label{struct_d_m_a_m_u_x___channel_status___type_def}\index{DMAMUX\_ChannelStatus\_TypeDef@{DMAMUX\_ChannelStatus\_TypeDef}}
\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a_m_u_x___channel_status___type_def_a2b806557d4176378c888423e1d4bdecc}{CSR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a_m_u_x___channel_status___type_def_acafeb4de92a6d63af5cfb33057555ee0}{CFR}}
\end{DoxyCompactItemize}


\label{doc-variable-members}
\Hypertarget{struct_d_m_a_m_u_x___channel_status___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_d_m_a_m_u_x___channel_status___type_def_acafeb4de92a6d63af5cfb33057555ee0}\index{DMAMUX\_ChannelStatus\_TypeDef@{DMAMUX\_ChannelStatus\_TypeDef}!CFR@{CFR}}
\index{CFR@{CFR}!DMAMUX\_ChannelStatus\_TypeDef@{DMAMUX\_ChannelStatus\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CFR}{CFR}}
{\footnotesize\ttfamily \label{struct_d_m_a_m_u_x___channel_status___type_def_acafeb4de92a6d63af5cfb33057555ee0} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMAMUX\+\_\+\+Channel\+Status\+\_\+\+Type\+Def\+::\+CFR}

DMA Channel Clear Flag Register \Hypertarget{struct_d_m_a_m_u_x___channel_status___type_def_a2b806557d4176378c888423e1d4bdecc}\index{DMAMUX\_ChannelStatus\_TypeDef@{DMAMUX\_ChannelStatus\_TypeDef}!CSR@{CSR}}
\index{CSR@{CSR}!DMAMUX\_ChannelStatus\_TypeDef@{DMAMUX\_ChannelStatus\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CSR}{CSR}}
{\footnotesize\ttfamily \label{struct_d_m_a_m_u_x___channel_status___type_def_a2b806557d4176378c888423e1d4bdecc} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMAMUX\+\_\+\+Channel\+Status\+\_\+\+Type\+Def\+::\+CSR}

DMA Channel Status Register 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
